¹Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore

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Abstract—Most asynchronous processor Instruction Set Architectures (ISA) are based on a single type of underlying asynchronous circuit design style. Asynchronous processor ISAs are entirely dependent on the type of asynchronous design style chosen and can support a limited set of simple applications only. Design reuse is typically difficult to realize in such cases. In this paper, we show a behavioral model of a predictor circuit system that configures an application profile-driven asynchronous processor ISA comprising two asynchronous design styles. The predictor circuit system is used to translate application profile and multi-radio code to the processor datapath through a compiler back-end. The target is an asynchronous processor that does not run an operating system and is used both as a complement and alternate to software-defined radios with high degrees of design reuse.

Index Terms—asynchronous processor, ISA, predictor circuit, multi-radio, compiler back-end, design reuse

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Cite: Dipnarayan Guha, Thambipillai Srikanthan, "Compiler back end design for translating multiradio descriptions to operating system-less asynchronous processor datapaths," Journal of Computers vol. 3, no. 1, pp. 7-14, 2008.